अमूर्त

Tuning of PID controller using multiple dominant poleplacement technique for stable third order processes

Ch. V. Naga Sowjanya

The current study proposes PID controller tuning for stable Third Order plus Time Delay (TOPTD) and Third Order plus Time Delay with a Zero (TOPTDZ) systems. The Multiple Dominant Pole Placement (MDP) Method is used to build the PID Controller. The performance of the suggested Controller is evaluated utilising errors such as Integral Square Error (ISE), Integral Absolute Error (IAE), and Integral Time Absolute Error (ITAE) on linear models of TOPTD and TOPTDZ and non-linear models such as isothermal CSTR and bio-reactor (ITAE). Using Kharitonov's theorem, the performance under model uncertainty is also seen when one parameter is perturbed at a time. The proposed MDPPID controller is compared to controllers built using performance specifications such as Overshoot (Shamsuzzoha 2013), IMC technique (Zhi-cheng et al., 2010; Shamsuzzoha and Lee, 2007), and Direct Synthesis Method (DSM) for stable TOPTD/TOPTDZ systems (Chidambaram, 1998; Chen and Seborg, 2002; Seshagiri rao Chidambaram,2006) and for model uncertainty. The efficiency of the suggested technique is demonstrated by simulation results on a variety of case studies of stable TOPTD, TOPTDZ, and non-linear models, which indicate that the proposed MDP-PID controller outperforms the other methods.

For decades, the omnipresent PID controller has been the most frequently used process control method. Although sophisticated control approaches such as model predictive control can give substantial benefits, for the great majority of industrial control loops, a well-designed and tuned PID controller has shown to be sufficient. The vast literature on PID controllers covers a wide range of design and tuning techniques based on various performance criteria. 3-6 Ziegler and Nichols (ZN)7 and Cohen and Coon (CC)7 described two early and well-known design approaches. 8 Both techniques were created to offer a quarter decay ratio closed-loop response.  Design relations based on integral error criteria9-11, as well as gain and phase margin formulas, are other well-known formulae for PI controller design. 12 PID controllers are commonly designed using a time-domain or frequency-domain performance criterion. The relationships between the closed-loop system's dynamic behaviour and these performance indices, on the other hand, are not straightforward. The controller design in the direct synthesis (DS) approach13-15, on the other hand, is based on a desired closed-loop transfer function. The controller is then analytically computed so that the closed-loop set-point response is identical to the desired response. The direct synthesis technique has the apparent benefit of including performance criteria directly through the design of the closed-loop transfer function. Choosing closed-loop poles is one approach to specify the closed-loop transfer function. It's based on a first-order plus time delay model with a significant time delay